The present invention is in the field of integrated circuit networks and more particularly directed to charge domain processing networks.
The need for transmitting data representative of an image through a relatively low data-rate channel is the driving force for the development of video bandwidth compression techniques. There are two basic classes of video compression algorithms: intraframe and interframe coding. Intraframe coders are effective to remove spatial redundancy from within respective video frames. Interframe coders generally use some form of predictive coding based on the information in a previous frame to remove redundancy between frames. Tremendous advantages are gained by incorporating motion detection and compensation (MDC) in an interframe coder. This is due to the fact that, in an area where motion is occurring, a better prediction can be formed based on the direction of motion. Transform image coding based on the discrete cosine transform (DCT) algorithm has been shown to provide good-quality, low-bit-rate image transmission. A hybrid interframe/intraframe coder offers the potential for achieving a higher bit-rate reduction.
Devices implementing such techniques are particularly advantageous, for example, in high-definition television (HDTV) receivers capable of accommodating different transmission formats and different field rates, and for low-bit-rate video communications in general. In video receivers, the use of MDC permits implementation of efficient interpolation algorithms to reconstruct missing fields following the use of temporal subsampling to reduce transmission bandwidth.
In automatic target tracking applications of video systems, it is important to detect the displacement of objects between pairs of successive image frames. Such signal processing generally requires a real-time motion detection and estimation (MDE) device for optimum performance.
The development of improved television systems is presently being limited by the use of different field rate standards. At present, there are three international television standards: the National Television System Committee (NTSC), the Phase Alternating Line (PAL) and the Sequential Couleur a Memoire (SECAM). The problem of frame conversion between different standards arises when there is no integral relationship between the two field rates; it is necessary to construct pictures for intermediate times. Linear interpolation without motion compensation would degrade the picture quality. While motion-compensated transcoding between
and NTSC has become technically quite successful, the transcoders are very expensive because temporal interpolation is required. The luminance resolution of the future HDTV is at least four times better than the NTSC system; to transcode such a high resolution video between different standards requires a temPoral interpolation processor capable of performing more than 16 billion operations/s. The availability of a low-cost field-rate converter would considerably simplify the trade-offs between different transmission formats.
An important aspect of most efficient MDC and MDE techniques is the applying a full search block matching algorithm (BMA) to an array of signal elements representative of an image frame. The BMA effectively passes a subarray, or template, of data values over the larger full array and identifies the particular location of the subarray which provides the highest spatial correlation (i.e. best match) of the subarray to the underlying array. In typical applications, the full array may be a 31.times.31 pixel rectangular array, and the template may be a 16.times.16 pixel rectangular array. By way of example, the computational requirement for motion compensation coding with a 16.times.16 full-search BMA is 3.8 billion computations/s for present NTSC video, and is expected to be on the order of 16 billion computations/s for future HDTV signals. For a digital HDTV transmitter and receiver, this computation rate requirement is near the upper limit of present digital technology, and consequently would result in highly complex and correspondingly costly equipment.
Accordingly, it is an object of the present invention to provide an improved charge domain processing network.
Another object is to provide a charge domain full search block matching algorithm processing system.